Sunday, January 16, 2011

HDL Programming for 4 bit Comparator

VHDL File Name:

comparator4bit.vhd
--Comparator4bit - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity comparator4bit is
Port ( a_in : in  STD_LOGIC_VECTOR (3 downto 0);
b_in : in  STD_LOGIC_VECTOR (3 downto 0);
g_op : out  STD_LOGIC;
e_op : out  STD_LOGIC;
l_op : out  STD_LOGIC);
end comparator4bit;
architecture Behavioral of comparator4bit is
begin
process(a_in,b_in)
begin
if( a_in > b_in) then
g_op <= '1';
e_op <= '0';
l_op <= '0';
elsif(a_in = b_in) then
g_op <= '0';
e_op <= '1';
l_op <= '0';
elsif(a_in < b_in) then
g_op <= '0';
e_op <= '0';
l_op <= '1';
else
g_op <= 'Z';
e_op <= 'Z';
l_op <= 'Z';
end if;
end process;
end Behavioral;

Verilog File Name:

comparator4bit.v
// Comparator 4bit
module comparator4bit( a_in,b_in,g_op,l_op,e_op);
input [3:0] a_in,b_in;
output g_op,l_op,e_op;
wire [3:0] a_in,b_in;
reg g_op,l_op,e_op;
always@(en,a_in,b_in)
if( a_in > b_in)
begin
g_op = 1;
l_op = 0;
e_op = 0;
end
else if( a_in < b_in)
begin
g_op = 0;
l_op = 1;
e_op = 0;
end
else if( a_in == b_in)
begin
g_op = 0;
l_op = 0;
e_op = 1;
end
else
begin
g_op = 1'bZ;
l_op = 1'bZ;
e_op = 1'bZ;
end
endmodule

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