Sunday, January 16, 2011

HDL Programming for 8 to 1 Multiplexer

VHDL File Name:

mux8to1.vhd
--mux8to1 - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity mux8to1 is
Port ( en : in  STD_LOGIC;
sel : in  STD_LOGIC_VECTOR (2 downto 0);
i_in : in  STD_LOGIC_VECTOR (7 downto 0);
y_out : out  STD_LOGIC);
end mux8to1;
architecture Behavioral of mux8to1 is
begin
process(en,sel,i_in)
begin
-- Active Low Enabled
if( en /= '0') then
y_out <= 'Z';
else
case sel is
when "000" => y_out <= i_in(0);
when "001" => y_out <= i_in(1);
when "010" => y_out <= i_in(2);
when "011" => y_out <= i_in(3);
when "100" => y_out <= i_in(4);
when "101" => y_out <= i_in(5);
when "110" => y_out <= i_in(6);
when "111" => y_out <= i_in(7);
when others => y_out <= 'Z';
end case;
end if;
end process;
end Behavioral;

Verilog File Name:

mux8to1.v
// Multiplexer 8 to 1
module mux8to1(en,i_in,sel,y_out);
input en;
input [2:0] sel;
input [7:0] i_in;
output y_out;
wire en;
wire [7:0] i_in;
wire [2:0] sel;
reg y_out;
always@(en,sel,i_in)
begin
if(en != 0)  // Active Low Enabled
y_out = 1'bZ;
else
begin
case(sel)
3'b000: y_out = i_in[0];
3'b001: y_out = i_in[1];
3'b010: y_out = i_in[2];
3'b011: y_out = i_in[3];
3'b100: y_out = i_in[4];
3'b101: y_out = i_in[5];
3'b110: y_out = i_in[6];
3'b111: y_out = i_in[7];
default: y_out = 1'bZ;
endcase
end
end
endmodule

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