**VHDL File Name:**encd_w_prior.vhd

-- encd_w_prior - Dataflow

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity encd_w_prior is

Port ( en : in STD_LOGIC;

a_in : in STD_LOGIC_VECTOR (7 downto 0);

y_op : out STD_LOGIC_VECTOR (2 downto 0));

end encd_w_prior;

architecture Dataflow of encd_w_prior is

begin

y_op <= "ZZZ" when en = '1' else -- Active Low Enabled

"111" when a_in(7)='1' else

"110" when a_in(6)='1' else

"101" when a_in(5)='1' else

"100" when a_in(4)='1' else

"011" when a_in(3)='1' else

"010" when a_in(2)='1' else

"001" when a_in(1)='1' else

"000" when a_in(0)='1' else

"ZZZ";

end Dataflow;

**Verilog File Name:**encd_w_prior.v

// encoder with priority

module encd_w_prior( en, a_in, y_op );

input en;

input [7:0] a_in;

output [2:0] y_op;

wire en;

wire [7:0] a_in;

reg [2:0] y_op;

always @ (a_in, en)

begin

if (en == 1'b1) // Active Low Enabled

y_op = 3'bZZZ;

else

begin

if(a_in[7] == 1'b1) y_op = 3'b111;

else if(a_in[6] == 1'b1) y_op = 3'b110;

else if(a_in[5] == 1'b1) y_op = 3'b101;

else if(a_in[4] == 1'b1) y_op = 3'b100;

else if(a_in[3] == 1'b1) y_op = 3'b011;

else if(a_in[2] == 1'b1) y_op = 3'b010;

else if(a_in[1] == 1'b1) y_op = 3'b001;

else if(a_in[0] == 1'b1) y_op = 3'b000;

else y_op = 3'bZZZ;

end

end

endmodule

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