Sunday, January 16, 2011

HDL programming for Encoder without Priority

VHDL File Name:

encd_wo_prior.vhd
-- encoder without priority - Behavioral
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity encd_wo_prior is
Port ( en  : in  STD_LOGIC;
a_in : in  STD_LOGIC_VECTOR (7 downto 0);
y_op : out  STD_LOGIC_VECTOR (2 downto 0));
end encd_wo_prior;
architecture Behavioral of encd_wo_prior is
begin
process (en,a_in)
begin
if(en /= '0') then   -- Active Low Enabled
y_op <= "ZZZ";
else
case a_in is
when "00000001" => y_op <= "000";
when "00000010" => y_op <= "001";
when "00000100" => y_op <= "010";
when "00001000" => y_op <= "011";
when "00010000" => y_op <= "100";
when "00100000" => y_op <= "101";
when "01000000" => y_op <= "110";
when "10000000" => y_op <= "111";
when  others    => y_op <= "ZZZ";
end case;
end if;
end process;
end Behavioral;

Verilog File Name:

encd_wo_prior.v
// encoder without priority
module encd_wo_prior( en, a_in, y_op );
input en;
input [7:0] a_in;
output [2:0] y_op;
wire en;
wire [7:0] a_in;
reg [2:0] y_op;
always @ (a_in, en)
begin
if(en) //Active Low Enabled
y_op = 3'bZZZ;
else
begin
case (a_in)
8'b00000001 : y_op = 3'b000;
8'b00000010 : y_op = 3'b001;
8'b00000100 : y_op = 3'b010;
8'b00001000 : y_op = 3'b011;
8'b00010000 : y_op = 3'b100;
8'b00100000 : y_op = 3'b101;
8'b01000000 : y_op = 3'b110;
8'b10000000 : y_op = 3'b111;
default  : y_op = 3'bZZZ;
endcase
end
end
endmodule

No comments:

Post a Comment

Related Posts Plugin for WordPress, Blogger...

Search On Flipkart

Facebook Connect