Sunday, January 16, 2011

HDL Programming for Full Adder

Full Adder Data Flow Description

VHDL File Name:

FullAdder_DF.vhd
-- FullAdder_DF - Data_Flow
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity FullAdder_DF is
Port ( a_in, b_in, c_in : in  STD_LOGIC;
sum, carry : out  STD_LOGIC);
end FullAdder_DF;
architecture Data_Flow of FullAdder_DF is
begin
sum <= a_in xor b_in xor c_in;
carry <= (a_in and b_in) or (b_in and c_in) or (a_in and c_in);
end Data_Flow;

Verilog File Name:

FullAdder_DF.v
// FullAdder - Data Flow Model
module FullAdder_DF( a_in, b_in, c_in, sum, carry );
input a_in, b_in, c_in;
output sum, carry;
assign sum = a_in ^ b_in ^ c_in;
assign carry = (a_in & b_in) | (b_in & c_in) | (c_in &
a_in);
endmodule

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